1. Field of the Invention
The present invention relates to a charge detecting device applied to a solid-state imaging apparatus such as a charge-coupled device (CCD) sensor, a complementary metal oxide semiconductor (CMOS) sensor, and the like.
2. Description of the Related Art
Typical examples of a solid-state imaging apparatus include a CCD sensor composed of a photodiode and a CCD shift register, and a CMOS sensor such as an active pixel sensor (APS) composed of a photodiode and a MOS transistor.
The APS includes a photodiode, a MOS switch, an amplifier for amplifying a signal from the photodiode, and the like on a pixel basis, and has a number of merits of enabling “XY addressing”, “integrating a sensor and a signal processing circuit into one chip”, etc. However, on the other hand, the APS has problems of a small pixel opening ratio and difficulty in reducing a chip size that determines the size of an optical system, due to the large number of elements per pixel. Thus, CCD sensors occupy a large part of the market.
Recently, due to the enhancement of a miniaturization technique of a MOS transistor and the increasing demand for “integrating a sensor and a signal processing circuit into one chip” and “reducing power consumption”, the APS is drawing attention.
FIG. 4A is a view showing a cross-sectional configuration of a semiconductor and a configuration of an output circuit of a photoelectric converter in a conventional APS (e.g., see JP 9(1997)-232555 A). The configuration of this conventional example will be described briefly below. In FIG. 4A, the photoelectric converter (photodiode) is of a PN junction type in which an N(N+) layer 402 is formed on the surface of a so-called P-type semiconductor substrate 401, and is composed of a diffusion floating region that also functions as a charge accumulating portion. Reference numeral 403 denotes a reset MOS transistor for resetting the diffusion floating region to a predetermined voltage (supply voltage VCC) in accordance with a reset control signal applied to a reset electrode 404; 405 denotes an amplifying MOS transistor (source follower circuit) for amplifying a voltage in the diffusion floating region; 406 denotes a row-selecting MOS transistor; and 407 denotes an output terminal. In FIG. 4A, broken lines represent the ends of a depletion layer.
Next, the outline of an operation of the photodiode thus configured will be described. The diffusion floating region previously is reset to a predetermined voltage (supply voltage VCC). When light is incident upon the photodiode, electrons generated by photoelectric conversion are accumulated in an N-layer 402 of the photodiode. An accumulated charge Q is converted to a voltage by a capacitance Cfd in the diffusion floating region, and the voltage in the diffusion floating region is decreased by a voltage corresponding to Q/Cfd from the reset voltage. This change in voltage is output from the output terminal 407 via the amplifying MOS transistor 405 and the row-selecting MOS transistor 406 in the case where the reset MOS transistor 403 is in an OFF state, and the row-selecting MOS transistor 406 is in an ON state.
However, in the configuration of the conventional example, the capacitance Cfd in the diffusion floating region corresponding to a charge/voltage converting portion is increased when the impurity concentration of the P-type semiconductor substrate (P-type well) 401 is increased with the miniaturization of a MOS transistor. Therefore, there is a problem that a conversion efficiency (Q/Cfd) is decreased, and an output voltage is lowered.
FIG. 4B is a graph showing the voltage dependency of the capacitance Cfd in the floating diffusion region. A horizontal axis represents an applied voltage V, and a vertical axis represents the capacitance Cfd. In FIG. 4B, during reset, the applied voltage is close to the supply voltage VCC, and a signal is not output from the output terminal 407.
As is understood from FIG. 4B, when the applied voltage V is increased, the capacitance Cfd can be reduced, and the conversion efficiency (Q/Cfd) can be enhanced. However, the increase in the applied voltage V results in an increase in the supply voltage VCC. This contradicts the decrease in voltage that is required in a miniaturized MOS transistor, which makes it impossible to satisfy transistor characteristics.
Furthermore, when a usable range ΔCfd of the capacitance Cfd is defined so as to suppress a change in a conversion efficiency, which is involved in a change in the applied voltage V, in a predetermined range, the dynamic range of an output voltage becomes narrow. In contrast, when it is attempted to keep a predetermined dynamic range, a change amount of the capacitance Cfd with respect to the change in the applied voltage V is large, and the output voltage fluctuates greatly with respect to a signal charge amount. More specifically, the linearity of a conversion efficiency is degraded.